1. Field of the Invention
The present invention relates to a memory system and a computer system.
2. Description of the Related Art
As memory systems used for computer systems, a solid state drive (SSD) mounted with a nonvolatile semiconductor memory such as a NAND flash memory (hereinafter simply referred to as “NAND memory”) attracts attention. The memory systems such as the SSD have advantages such as high speed and light weight compared with magnetic disk devices.
In general, a memory system is mounted with a plurality of (e.g., sixteen or thirty-two) NAND memory chips (hereinafter simply referred to as “chips”) to increase a memory capacity. Each of the chips individually has a control circuit that controls a column decoder, a row decoder, and the like for accessing memory cells. When the control circuit fails, no data written in the chip can be read out. Control circuits of the chips are required that a fraction defective is about 1/n (n is the number of mounted chips) times or less as small as a fraction defective allowed for the entire memory system. Because the number of chips mounted on the memory system tends to increase, it is anticipated that a fraction defective allowed per one chip, which decreases in inverse proportion to the number of chips, makes memory system manufacturing more difficult in the future. Therefore, it is demanded to relax the fraction defective allowed for each single chip. There is also a demand for a mechanism to remedy data readout-disabled when the control circuit fails.
As measures to meet these demands, it is conceivable to impart redundancy to the number of chips and store an error correction code in a redundant chip. However, chips of a nonvolatile semiconductor memory have a limit in the number of times of writing and erasing. When a specific chip is used exclusively for the error correction code, erasing and rewriting are repeated every time any one of the other chips is rewritten. Therefore, deterioration of the chip exclusively used for the error correction code is worsened.
There are several publicly-known technologies for calculating an error correction code based on data stored in a storage element and, when an error occurs in the stored data, remedying the data based on the error correction code calculated in advance. For example, Japanese Patent Application Laid-Open No. 2007-323224 discloses a technology for forming a parity group with a plurality of chips. However, Japanese Patent Application Laid-Open No. 2007-323224 does not describe redundancy of the number of chips and a position where a parity is stored. Japanese Patent Application Laid-Open No. 2001-167002 discloses a technology for storing, in a semiconductor memory element, an error correction code concerning data stored in a disk area of the semiconductor memory element. Japanese Patent Application Laid-Open No. 2000-339228 discloses a technology including a dedicated memory card that stores parity information. However, deterioration of a section where the error correction code is stored cannot be suppressed by the technologies disclosed in Japanese Patent Application Laid-Open Nos. 2001-167002 and 2000-339228.